XRT75R03D_06 Datasheet, PDF (126/135 Pages) Exar Corporation – EXAR DATA SHEET FORMAT TEMPLATES

XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.4
• If the XRT75R03D has been configured to operate in the Host Mode
The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers to
1, as illustrated below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7
BIT 6
Unused
R/O
R/O
0
0
BIT 5
PRBS Enable
Ch_n
R/W
0
BIT 4
RLB_n
R/W
0
BIT 3
LLB_n
R/W
0
BIT 2
E3_n
R/W
0
BIT 1
STS-1/
DS3_n
R/W
0
BIT 0
SR/DR_n
R/W
1
• If the XRT75R03D has been configured to operate in the Hardware Mode
Then the user should tie pin 65 (SR/DR*) to "High".
c. Configure each of the three channels within the XRT75R03D to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
• If the XRT75R03D has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA1) to "0" and Bit D0 (JA0) to "1", within the Jitter Attenuator Control
Register, as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
0
1
• If the XRT75R03D has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".
Once the user accomplishes either of these steps, then the Jitter Attenuator (within the XRT75R03D) will be
configured to operate with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of three three channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
• If the XRT75R03D has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
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