LM3S2110 Datasheet, PDF (81/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0110.709F
31
30
29
28
27
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
15
14
13
12
11
MINSYSDIV
Type RO
RO
RO
RO
RO
Reset
0
1
1
1
0
26
25
RO
RO
0
0
10
9
reserved
RO
RO
0
0
24
CAN0
RO
1
8
RO
0
23
22
21
reserved
RO
RO
RO
0
0
0
7
MPU
RO
1
6
5
reserved
RO
RO
0
0
20
PWM
RO
1
4
PLL
RO
1
19
RO
0
3
WDT
RO
1
18
17
reserved
RO
RO
0
0
2
SWO
RO
1
1
SWD
RO
1
16
RO
0
0
JTAG
RO
1
Bit/Field
31:25
24
23:21
20
19:16
15:12
Name
reserved
CAN0
reserved
PWM
reserved
MINSYSDIV
Type
RO
RO
RO
RO
RO
RO
Reset
0
1
0
1
0
0x7
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module Present
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x7 Specifies a 25-MHz clock with a PLL divider of 8.
11:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
November 29, 2007
81
Preliminary