LM3S2110 Datasheet, PDF (106/485 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
15
14
13
12
11
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
26
25
RO
RO
0
0
10
9
reserved
RO
RO
0
0
24
CAN0
R/W
0
8
RO
0
23
22
21
reserved
RO
RO
RO
0
0
0
7
6
5
RO
RO
RO
0
0
0
20
PWM
R/W
0
4
RO
0
19
RO
0
3
WDT
R/W
0
18
17
16
reserved
RO
RO
RO
0
0
0
2
1
0
reserved
RO
RO
RO
0
0
0
Bit/Field
31:25
24
23:21
20
19:4
3
2:0
Name
reserved
CAN0
reserved
PWM
reserved
WDT
reserved
Type
RO
R/W
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Reset Control
Reset control for CAN unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Reset Control
Reset control for PWM module.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Reset Control
Reset control for Watchdog unit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
106
November 29, 2007
Preliminary