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LM3S2110 Datasheet, PDF (24/485 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
⢠Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
⢠Produces two independent PWM signals
â Dead-band generator
⢠Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
⢠Can be bypassed, leaving input PWM signals unmodified
â Flexible output control block with PWM output enable of each PWM signal
⢠PWM output enable of each PWM signal
⢠Optional output inversion of each PWM signal (polarity control)
⢠Optional fault handling for each PWM signal
⢠Synchronization of timers in the PWM generator blocks
⢠Synchronization of timer/comparator updates across the PWM generator blocks
⢠Interrupt status summary of the PWM generator blocks
â GPIOs
â 11-40 GPIOs, depending on configuration
â 5-V-tolerant input/outputs
â Programmable interrupt generation as either edge-triggered or level-sensitive
â Bit masking in both read and write operations through address lines
â Programmable control for GPIO pad configuration:
⢠Weak pull-up or pull-down resistors
⢠2-mA, 4-mA, and 8-mA pad drive
⢠Slew rate control for the 8-mA drive
⢠Open drain enables
⢠Digital input enables
â Power
â On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
â Low-power options on controller: Sleep and Deep-sleep modes
â Low-power options for peripherals: software controls shutdown of individual peripherals
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November 29, 2007
Preliminary
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