LM3S2110 Datasheet, PDF (14/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 203
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 204
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 205
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 206
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 207
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 208
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 209
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 210
Watchdog Timer ........................................................................................................................... 211
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 214
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 215
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 216
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 217
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 218
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 219
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 220
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 221
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 222
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 223
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 224
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 225
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 226
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 227
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 228
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 229
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 230
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 231
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 232
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 233
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 234
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 242
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 244
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 246
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 248
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 249
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 250
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 251
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 253
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 255
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 257
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 259
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 260
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 261
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 263
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 264
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 265
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 266
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 267
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November 29, 2007
Preliminary