LM3S2110 Datasheet, PDF (414/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 415).
The PWM generator interrupts simply reflect the status of the PWM generator; they are cleared via
the interrupt status register in the PWM generator block. Bits set to 1 indicate the events that are
active; a zero bit indicates that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
IntFault
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntPWM0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
15:1
0
Name
reserved
IntFault
reserved
IntPWM0
Type
RO
RO
RO
RO
Reset
0x00
0
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Interrupt Asserted
Indicates that the fault input has been asserted.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
414
November 29, 2007
Preliminary