LM3S2110 Datasheet, PDF (454/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Electrical Characteristics
20.2.3
20.2.4
Parameter Name
Motional inductance (typ)
14.3
Equivalent series resistance (max) 120
Shunt capacitance (max)
10
Load capacitance (typ)
16
Drive level (typ)
100
Value
19.1 28.6
160 200
10
10
16
16
100 100
Units
32.7 mH
220 Ω
10
pF
16
pF
100 µW
Analog Comparator
Table 20-9. Analog Comparator Characteristics
Parameter Parameter Name
Min Nom Max Unit
V_OS Input offset voltage
- ±10 ±25 mV
V_CM Input common mode voltage range
0 - V_DD-1.5 V
C_MRR Common mode rejection ratio
50 -
T_RT Response time
--
T_MC Comparator mode change to Output Valid - -
- dB
1 µs
10 µs
Table 20-10. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name
Min Nom Max Unit
R_HR Resolution high range
- V_DD/32 - LSB
R_LR Resolution low range
- V_DD/24 - LSB
A_HR Absolute accuracy high range -
- ±1/2 LSB
A_LR Absolute accuracy low range -
- ±1/4 LSB
I²C
Table 20-11. I²C Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH Start condition hold time
36 -
-
system clocks
I2^a
t_LP
Clock Low period
36 -
-
system clocks
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
454
November 29, 2007
Preliminary