LM3S2110 Datasheet, PDF (13/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
Register 15:
Register 16:
Register 17:
Register 18:
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 130
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 131
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 132
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 133
General-Purpose Input/Outputs (GPIOs) ................................................................................... 134
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 141
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 142
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 143
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 144
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 145
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 146
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 147
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 148
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 149
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 150
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 152
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 153
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 154
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 155
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 156
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 157
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 158
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 159
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 160
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 161
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 163
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 164
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 165
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 166
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 167
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 168
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 169
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 170
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 171
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 172
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 173
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 174
General-Purpose Timers ............................................................................................................. 175
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 187
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 188
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 190
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 192
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 195
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 197
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 198
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 199
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 201
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 202
November 29, 2007
13
Preliminary