LM3S2110 Datasheet, PDF (356/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Controller Area Network (CAN) Module
Parameter Range Remark
SJW
[1 .. 4] t_q May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. The sum
of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte,
and SJW and BRP are combined in the other byte.
In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be
programmed to a numerical value that is one less than its functional value; so instead of values in
the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW
(functional range of [1..4]) is represented by only two bits. Therefore, the length of the bit time is
(programmed values):
[TSEG1 + TSEG2 + 3] tq
or (functional values):
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq
The data in the bit timing registers are the configuration input of the CAN protocol controller. The
Baud Rate Prescalar (configured by BRP) defines the length of the time quantum, the basic time
unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. It generates and discards the enclosing
fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the
error management, and decides which type of synchronization is to be used. It is evaluated at the
Sample Point and processes the sampled bus input bit. The time after the Sample Point that is
needed to calculate the next bit to be sent (that is, the data bit, CRC bit, stuff bit, error flag, or idle)
is called the Information Processing Time (IPT).
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase_Seg2. In case of synchronization, Phase_Seg2
may be shortened to a value less than IPT, which does not affect bus timing.
14.4.15
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the desired bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times
measured in the system. A maximum bus length as well as a maximum node delay has to be defined
for expandable CAN bus systems. The resulting time for Prop_Seg is converted into time quanta
(rounded up to the nearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), which leaves (bit time - Prop_Seg - 1) tq for the two Phase
Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same
length, that is, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
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November 29, 2007
Preliminary