LM3S2110 Datasheet, PDF (15/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 268
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 269
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 270
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 271
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 272
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 273
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 274
Synchronous Serial Interface (SSI) ............................................................................................ 275
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 287
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 289
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 291
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 292
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 294
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 295
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 297
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 298
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 299
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 300
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 301
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 302
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 303
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 304
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 305
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 306
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 307
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 308
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 309
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 310
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 311
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 312
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 326
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 327
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 331
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 332
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 333
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 334
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 335
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 336
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 337
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 339
I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 340
I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 342
I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 343
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 344
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 345
I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 346
November 29, 2007
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Preliminary