LM3S2110 Datasheet, PDF (441/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
Table 18-2. Signals by Signal Name
Pin Name
C0+
C0-
C0o
C1+
C1-
C2+
C2-
CAN0Rx
CAN0Tx
CCP0
CCP1
CCP2
CCP3
CMOD0
Pin Number
90
92
100
24
91
23
22
10
11
66
34
67
95
65
Pin Type
I
I
O
I
I
I
I
I
O
I/O
I/O
I/O
I/O
I/O
CMOD1
76
I/O
Fault
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
99
I
9
-
15
-
21
-
33
-
39
-
45
-
54
-
57
-
63
-
69
-
82
-
87
-
94
-
4
-
GNDA
97
-
I2C0SCL
I2C0SDA
70
I/O
71
I/O
Buffer Type Description
Analog Analog comparator 0 positive input
Analog Analog comparator 0 negative input
TTL
Analog comparator 0 output
Analog Analog comparator positive input
Analog Analog comparator 1 negative input
Analog Analog comparator positive input
Analog Analog comparator 2 negative input
TTL
CAN module 0 receive
TTL
CAN module 0 transmit
TTL
Capture/Compare/PWM 0
TTL
Capture/Compare/PWM 1
TTL
Capture/Compare/PWM 2
TTL
Capture/Compare/PWM 3
TTL
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTL
PWM Fault
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
OD
I2C module 0 clock
OD
I2C module 0 data
November 29, 2007
441
Preliminary