LM3S2110 Datasheet, PDF (137/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.1.3
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 150), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.1.4
Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 150) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 160) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 161) have been set to 1.
8.1.5
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
8.1.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 137
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-2 on page 138 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Input
0
0
1
1
(GPIO)
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
PUR
?
?
X
X
X
PDR
?
?
X
X
X
DR2R
X
?
X
?
?
DR4R
X
?
X
?
?
DR8R
X
?
X
?
?
SLR
X
?
X
?
?
November 29, 2007
137
Preliminary