20-101-1051 Datasheet, PDF (81/165 Pages) List of Unclassifed Manufacturers – C-Programmable Core Module with NAND Flash Mass Storage and Ethernet

Table A-4 lists the delays in gross memory access time at 3.3 V.
Table A-4. Data and Clock Delays VIN ±10%, Temp, -40°C–+85°C (maximum)
VIN
3.3 V
Clock to Address Output Delay
(ns)
30 pF
60 pF
90 pF
6
8
11
Data Setup
Time Delay
(ns)
1
Spectrum Spreader Delay
(ns)
Normal
Strong
no dbl/dbl no dbl/dbl
3/4.5
4.5/9
The measurements are taken at the 50% points under the following conditions.
• T = -40°C to 85°C, V = V_DD ±10%
• Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
• T_adr, the clock to address delay
• T_CSx, the clock to memory chip select delay
• T_IOCSx, the clock to I/O chip select delay
• T_IORD, the clock to I/O read strobe delay
• T_IOWR, the clock to I/O write strobe delay
• T_BUFEN, the clock to I/O buffer enable delay
The data setup time delays are similar for both T_setup and T_hold.
When both the spectrum spreader and the clock doubler are enabled, every other clock
cycle is shortened (sometimes lengthened) by a maximum amount given in the table
above. The shortening takes place by shortening the high part of the clock. If the doubler
is not enabled, then every clock is shortened during the low part of the clock period. The
maximum shortening for a pair of clocks combined is shown in the table.
Technical Note TN227, Interfacing External I/O with Rabbit 2000/3000 Designs, con-
tains suggestions for interfacing I/O devices to the Rabbit 3000 microprocessors.
User’s Manual
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