M0518 Datasheet, PDF (67/72 Pages) List of Unclassifed Manufacturers – 36/68 Kbytes flash, 8K bytes SRAM

NuMicro M0518 Series Datasheet
8.6 I²C Dynamic Characteristics
SYMBOL
PARAMETER
STANDARD MODE^[1][2]
MIN.
MAX.
FAST MODE^[1][2]
MIN.
MAX.
UNIT
tLOW
SCL low period
uS
tHIGH
SCL high period
uS
tSU; STA
Repeated START condition setup time
uS
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
tBUF
STOP condition setup time
Bus free time
4
-
0.6
-
uS
4.7^[3]
-
1.2^[3]
-
uS
tSU;DAT
tHD;DAT
Data setup time
Data hold time
250
-
100
0^[4]
3.45^[5]
0^[4]
-
nS
0.8^[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Note:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must be higher than 8 MHz to
achieve the maximum fast mode I²C frequency.
3. I²C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of
the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL
signal.
SDA
SCL
STOP
START
tBUF
tLOW
tHD;STA
tHIGH
tHD;DAT
tr
tf
tSU;DAT
Figure 8-4 I²C Timing Diagram
Repeated
START
tSU;STA
STOP
tSU;STO
Feb 08, 2017
Page 67 of 72
Revision 1.01