M0518 Datasheet, PDF (36/72 Pages) List of Unclassifed Manufacturers – 36/68 Kbytes flash, 8K bytes SRAM

NuMicro M0518 Series Datasheet
22.1184
MHz
4~24
MHz
10 kHz
22.1184 MHz
111
10 kHz
011
PLLFOUT
010
Reserved
001
4~24 MHz
000
CLKSEL0[2:0]
22.1184 MHz
1
4~24 MHz
0
PLLCON[19]
PLLFOUT
22.1184 MHz
1/2
111
HCLK
1/2
011
4~24 MHz
1/2
010
Reserved
001
4~24 MHz
000
CLKSEL0[5:3]
CPUCLK
1/(HCLK_N+1)
HCLK
22.1184 MHz
111
10 kHz
101
External trigger
011
HCLK
010
Reserved
001
4~24 MHz
000
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
PCLK
22.1184 MHz
CPUCLK
1
0
SYST_CSR[2]
PCLK
1
PLLFOUT
0
CLKSEL3[16]
CLKSEL3[17]
CLKSEL3[18]
CLKSEL3[19]
HCLK
CLKSEL2[17:16]
10 kHz
11
1/2048
10
CPU
ISP
I2C 0~1
TMR 3
TMR 2
TMR 1
TMR 0
FMC
SysTick
PWM 0
PWM 1
BPWM 0
BPWM 1
WWDT
22.1184 MHz
11
PLLFOUT
01
4~24 MHz
00
CLKSEL1[25:24]
22.1184 MHz
11
HCLK
10
PLLFOUT
01
4~24 MHz
00
CLKSEL1[3:2]
HCLK
1/2048
10 kHz
11
10
CLKSEL1[1:0]
HCLK
1
PLLFOUT
0
CLKSEL1[4]
22.1184 MHz
11
HCLK
10
Reserved
01
4~24 MHz
00
CLKSEL2[3:2]
1/(UART_N+1)
1/(ADC_N+1)
10 kHz
WDT
SPI 0
UART 0~5
ADC
BOD
FDIV
Figure 6-4 Clock Generator Global View Diagram
6.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-5.
Feb 08, 2017
Page 36 of 72
Revision 1.01