M0518 Datasheet, PDF (39/72 Pages) List of Unclassifed Manufacturers – 36/68 Kbytes flash, 8K bytes SRAM

NuMicro M0518 Series Datasheet
6.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from F_in/2¹ to F_in/2¹⁶ where Fin is input clock frequency to the clock
divider.
The output formula is F_out = F_in/2^(N+1), where F_in is the input clock frequency, F_out is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
22.1184 MHz
11
HCLK
10
Reserved
01
4~24 MHz
00
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
FRQDIV_CLK
Figure 6-7 Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
16 chained
divide-by-2 counter
FRQDIV_CLK
1/2 1/2² 1/2³ …... 1/2¹⁵ 1/2¹⁶
FSEL
(FRQDIV[3:0])
DIVIDER1
(FRQDIV[5])
0000
0001
: 16 to 1
:
MUX
1110
1111
0 ^CLKO
1
Figure 6-8 Frequency Divider Block Diagram
Feb 08, 2017
Page 39 of 72
Revision 1.01