M0518 Datasheet, PDF (23/72 Pages) List of Unclassifed Manufacturers – 36/68 Kbytes flash, 8K bytes SRAM

NuMicro M0518 Series Datasheet
6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex™-M0 Core
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
Cortex^TM-M0 Components
Cortex^TM-M0 processor
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Cortex^TM-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Bus Matrix
Debug
Breakpoint
and
Watchpoint
Unit
Debugger
Interface
Debug
Access
Port
(DAP)
AHB-Lite
Interface
Figure 6-1 Functional Controller Diagram
Serial Wire or
JTAG Debug Port
The implemented device provides the following components and features:
 A low gate count processor:
- ARMv6-M Thumb^® instruction set
- Thumb-2 technology
- ARMv6-M compliant 24-bit SysTick timer
- A 32-bit hardware multiplier
- System interface supported with little-endian data accesses
- Ability to have deterministic, fixed-latency, interrupt handling
- Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
- C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
- Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
Feb 08, 2017
Page 23 of 72
Revision 1.01