M0518 Datasheet, PDF (37/72 Pages) List of Unclassifed Manufacturers – 36/68 Kbytes flash, 8K bytes SRAM

NuMicro M0518 Series Datasheet
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
PLLFOUT
Reserved
4~24 MHz
011
CPUCLK
CPU
010
HCLK
1/(HCLK_N+1)
AHB
001
HCLK_N (CLKDIV[3:0])
PCLK
APB
000
CPU in Power Down Mode
Figure 6-5 System Clock Block Diagram
The clock source of SysTick in Cortex™-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-6.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
1/2
111
HCLK
1/2
011
4~24 MHz
1/2
010
Reserved
001
4~24 MHz
000
STCLK
Figure 6-6 SysTick Clock Control Block Diagram
Feb 08, 2017
Page 37 of 72
Revision 1.01