NUC951ADN Datasheet, PDF (565/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
32-BIT ARM926EJ-S BASED MCU
PS2 Host Controller Command Register (PS2CMD)
Register
PS2CMD
31
23
15
7
Address
0xB800_9x00
R/W
R/W
Description
Command register
30
29
22
21
14
13
RESERVED
6
5
28
27
RESERVED
20
19
RESERVED
12
11
DWAIT
RXROFF
4
3
PS2CMD
Reset Value
0x0000_0000
26
25
24
18
17
16
10
RXEOFF
2
9
TRAP_SHIFT
1
8
EnCMD
0
Bits
[12]
[11]
[10]
[9]
[8]
[7:0]
Descriptions
DWAIT
DATA Line Waiting Mode Register
1: To control the Data line pull low to wait the host read complete at receiving
0: Normal mode; For PS2 bar-code device, this bit is suggested to be 1.
RXROFF
Receive Released Key Checking OFF Register
1: Do not checking receive released key (0xF0), the interrupt will occur for the
released key (0xF0) when this bit is set.
0: Checking receive released key (0xF0), and no interrupt, ASCII and SCAN
code for the released key when this bit is clear.
This bit is clear by default. For PS2 mouse device, this bit must set to 1.
RXEOFF
Receive Extended Key Checking OFF Register
1: Do not checking receive extended key (0xE0), the interrupt will occur for the
extended key (0xE0) when this bit is set.
0: Checking receive extended key (0xE0), and no interrupt, ASCII and SCAN
code for the released key when this bit is clear.
This bit is clear by default. For PS2 mouse device, this bit must set to 1.
TRAP_SHIFT
Trap Shift Key Output to Scan Code Register
If the shift key scan code (0x12 0r 0x59) is received by host, software can
indicate host whether to update to scan code register or not. No ASCII or SCAN
codes will be reported for the shift keys if this bit is set. In this condition, host
will only report the shift keys at the Rx_shift_key bit of Status register and no
interrupt will occur for the shift keys. This is useful for those who wish to use
the ASCII data stream and don’t want to “manually” filter out the shift key
codes. This bit is clear by default. For PS2 mouse device, this bit must clear to
0.
EnCMD
Enable write PS2 Host Controller Commands
This bit enables the write function of Host controller command to device. Set
this bit will start the write process of PS2CMD content and hardware will
automatically clear this bit while write process is finished.
PS2CMD
PS2 Host Controller Commands
This command filed is sent by the Host to the Keyboard. The most common
Publication Release Date: Sep. 10, 2012
565
Revision: A5