NUC951ADN Datasheet, PDF (190/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
32-BIT ARM926EJ-S BASED MCU
[8]
PRST
Port Reset (R/W)
1=Port is in Reset. 0=Port is not in Reset. Default = 0. When software writes
a one to this bit (from a zero), the bus reset sequence as defined in the USB
Specification Revision 2.0 is started. Software writes a zero to this bit to
terminate the bus reset sequence. Software must keep this bit at a one long
enough to ensure the reset sequence, as specified in the USB Specification
Revision 2.0, completes. Note: when software writes this bit to a one, it must
also write a zero to the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay before
the bit status changes to a zero. The bit status will not read as a zero until
after the reset has completed. If the port is in high-speed mode after reset is
complete, the host controller will automatically enable this port (e.g. set the
Port Enable bit to a one). A host controller must terminate the reset and
stabilize the state of the port within 2 milliseconds of software transitioning
this bit from a one to a zero. For example: if the port detects that the
attached device is high-speed during reset, then the host controller must
have the port in the enabled state within 2ms of software writing this bit to a
zero.
The HCHalted bit in the USBSTS register should be a zero before software
attempts to use this bit. The host controller may hold Port Reset asserted to
a one when the HCHalted bit is a one.
This field is zero if Port Power is zero.
Suspend (R/W)
1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port
Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend] Port State
0X Disable
10 Enable
11 Suspend
When in suspend state, downstream propagation of data is blocked on this
port, except for port reset. The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In
[7]
Suspend
the suspend state, the port is sensitive to resume detection. Note that the bit
status does not change until the port is suspended and that there may be a
delay in suspending a port if there is a transaction currently in progress on
the USB.
A write of zero to this bit is ignored by the host controller. The host controller
will unconditionally set this bit to a zero when:
Software sets the Force Port Resume bit to a zero (from a one).
Software sets the Port Reset bit to a one (from a zero).
If host software sets this bit to a one when the port is not enabled (i.e.
Port enabled bit is a zero) the results are undefined.
This field is zero if Port Power is zero.
Publication Release Date: Sep. 10, 2012
190
Revision: A5