NUC951ADN Datasheet, PDF (453/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
32-BIT ARM926EJ-S BASED MCU
Framing Error Indicator
[3]
FEI
This bit is set to logic 1 whenever the received character does not have a valid "stop
bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic
0), and is reset whenever the CPU reads the contents of the LSR.
Parity Error Indicator
[2]
PEI
This bit is set to logic 1 whenever the received character does not have a valid
"parity bit", and is reset whenever the CPU reads the contents of the LSR.
Overrun Error Indicator
[1]
OEI
An overrun error will occur only after the Rx FIFO is full and the next character has
been completely received in the shift register. The character in the shift register is
overwritten, but it is not transferred to the Rx FIFO. OE is indicated to the CPU as
soon as it happens and is reset whenever the CPU reads the contents of the LSR.
Rx FIFO Data Ready
[0]
RFDR
0 = Rx FIFO is empty
1 = Rx FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the Rx FIFO.
These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not suggested).
Publication Release Date: Sep. 10, 2012
453
Revision: A5