NUC951ADN Datasheet, PDF (223/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
32-BIT ARM926EJ-S BASED MCU
Interrupt Enable Low Register (IRQ_ENB_L)
Register
IRQ_ENB_L
Address
0xB000_6008
R/W
Description
R/W Interrupt Enable Low Register
Default Value
0x0000_0001
31
23
15
7
EPF_IE
30
22
14
6
EPE_IE
29
21
13
5
EPD_IE
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
EPC_IE EPB_IE
26
18
10
2
EPA_IE
25
17
9
1
CEP_IE
24
16
8
0
USB_IE
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Descriptions
EPF_IE
Interrupt Enable for Endpoint F.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint F
EPE_IE
Interrupt Enable for Endpoint E.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint E
EPD_IE
Interrupt Enable for Endpoint D.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint D
EPC_IE
Interrupt Enable for Endpoint C.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint C
EPB_IE
Interrupt Enable for Endpoint B.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint B
EPA_IE
Interrupt Enable for Endpoint A.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the endpoint A.
CEP_IE
Control Endpoint Interrupt Enable.
When set, this bit enables a local interrupt to be generated when an
interrupt is pending for the control endpoint.
USB_IE
USB Interrupt Enable.
When set, this bit enables a local interrupt to be generated when a USB
event occurs on the bus.
Publication Release Date: Sep. 10, 2012
223
Revision: A5