NUC951ADN Datasheet, PDF (172/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
32-BIT ARM926EJ-S BASED MCU
EHCI Structural Parameters Register (EHCSPR)
Register
Address
EHCSPR 0xB000_5004
R/W
Description
R EHCI Structural Parameters Register
Reset Value
0x0000_0012
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
N_CC
N_PCC
7
6
5
4
3
2
1
0
Reserved
PPC
N_PORTS
Bits
[15:12]
[11:8]
[4]
Descriptions
N_CC
N_PCC
PPC
Number of Companion Controller
This field indicates the number of companion controllers associated with this
USB 2.0 host controller.
A zero in this field indicates there are no companion host controllers. Port-
ownership hand-off is not supported. Only high-speed devices are supported
on the host controller root ports.
A value larger than zero in this field indicates there are companion USB 1.1
host controller(s). Port-ownership hand-offs are supported. High, Full- and
Low-speed devices are supported on the host controller root ports.
Number of Ports per Companion Controller
This field indicates the number of ports supported per companion host
controller. It is used to indicate the port routing configuration to system
software.
For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then
N_PCC could have a value of 3. The convention is that the first N_PCC ports
are assumed to be routed to companion controller 1, the next N_PCC ports to
companion controller 2, etc. In the previous example, the N_PCC could have
been 4, where the first 4 are routed to companion controller 1 and the last
two are routed to companion controller 2.
The number in this field must be consistent with N_PORTS and N_CC.
Port Power Control
This field indicates whether the host controller implementation includes port
power control. A one in this bit indicates the ports have port power switches.
A zero in this bit indicates the port do not have port power stitches. The
value of this field affects the functionality of the Port Power field in each port
status and control register.
Publication Release Date: Sep. 10, 2012
172
Revision: A5