NUC951ADN Datasheet, PDF (155/590 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC951ADN
[17]
BLOCK
[13:12
]
TWS
[10]
D_INTS
[7]
SAFIX
[6]
DAFIX
[5]
SADIR
[4]
DADIR
[3:2] GDMAMS
[1]
BME
32-BIT ARM926EJ-S BASED MCU
Bus Lock
0 = Unlocks the bus during the period of transfer
1 = locks the bus during the period of transfer
Transfer Width Select
00 = One byte (8 bits) is transferred for every GDMA operation
01 = One half-word (16 bits) is transferred for every GDMA operation
10 = One word (32 bits) is transferred for every GDMA operation
11 = Reserved
The GDMA_SCRB and GDMA_DSTB should be alignment under the TWS
selection
Descriptor Fetch Mode Interrupt Select
0 = The interrupt will take place at every end of descriptor fetch transfer.
1 = The interrupt only take place at the last descriptor fetch transfer.
NOTE: this bit is only available in descriptor mode and lists intention.
Source Address Fixed
0 = Source address is changed during the GDMA operation
1 = Do not change the source address during the GDMA operation. This
feature can be used when data were transferred from a single source to
multiple destinations.
Destination Address Fixed
0 = Destination address is changed during the GDMA operation
1 = Do not change the destination address during the GDMA operation. This
feature can be used when data were transferred from multiple sources to a
single destination.
Source Address Direction
0 = Source address is incremented successively
1 = Source address is decremented successively
Destination Address Direction
0 = Destination address is incremented successively
1 = Destination address is decremented successively
GDMA Mode Select
00 = Software mode (Memory-to-Memory)
01 = External nXDREQ0 mode for external device(I/O-to-Memory)
10 = Reserved
11 = Reserved
Burst Mode Enable
0 = Disables the 8-data burst mode
1 = Enables the 8-data burst mode
FF there are 8 words to be transferred, and BME [1]=1, the GDMA_TCNT
should be 0x01;
However, if BME [1] =0, the GDMA_TCNT should be 0x08.
It has to set BME [1] = 0 for I/O device access.
Publication Release Date: Sep. 10, 2012
155
Revision: A5