W78IRD2 Datasheet, PDF (54/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
15. IN-SYSTEM PROGRAMMING (ISP) MODE
The W78IRD2 is equipped with 64 KB of main flash EPROM (AP Flash EPROM) for the application
program and 4 KB of auxiliary flash EPROM (LD Flash EPROM) for the loader program. In normal
operation, the microcontroller executes the code in the AP Flash EPROM. If the code in the AP Flash
EPROM needs to be modified, however, the W78IRD2 allows the program to activate the In-System
Programming (ISP) mode to modify it.
The contents in the AP Flash EPROM can be modified by setting the CHPCON register. The CHPCON
is read-only by default. The program must write two specific values, 87H and then 59H,
sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR
register with any other values disables the write attribute. Setting the bit CHPCON.0 makes the
W78IRD2 enter ISP mode when it wakes up from the next idle mode. It takes time to set this up in idle
mode, however, so the program may use a timer interrupt to wake up the W78IRD2 and enter ISP
mode after an appropriate amount of time in idle mode.
To change the contents in the AP Flash EPROM, the existing contents must set the CHPCON register
and then enter idle mode. When the W78IRD2 wakes up, it switches from AP Flash EPROM to LD
Flash EPROM, clears the program counter, pushing 0000H to the first 2 bytes of stack memory and
executes the interrupt service routine in the LD Flash EPROM. Therefore, the first execution of RETI
instruction will make the program jump to 00H in the LD Flash EPROM. When the AP Flash EPROM
has been updated, the W78IRD2 offers a software reset to switch back to the AP Flash EPROM.
Setting CHPCON bits 0, 1 and 7 to logic-1 creates a software reset to reset the CPU. A flowchart
for the LD Flash EPROM program is shown at the end of this section.
SFRAH, SFRAL: The objective address of the on-chip flash EPROM in ISP mode. SFRFAH contains
the high-order byte, and SFRFAL contains the low-order byte.
SFRFD: The program data in ISP mode.
SFRCN: The control byte for ISP mode.
SFRCN (C7)
BIT
NAME
FUNCTION
7
-
Reserve.
On-chip flash EPROM bank select for in-system programming.
6
WFWIN 0: 64-KB flash EPROM bank is the destination for re-programming.
1: 4-KB flash EPROM bank is the destination for re-programming.
5
OEN Flash EPROM output enable.
4
CEN Flash EPROM chip enable.
3, 2, 1, 0 CTRL[3:0] Flash EPROM control signals; see below.
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