W78IRD2 Datasheet, PDF (42/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
10.5 Framing Error Detection
A frame error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically, the frame error is due to noise or contention on the serial communication
line. The W78IRD2 has the ability to detect framing errors and set a flag which can be checked by
software.
The frame error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051
family. However, in the W78IRD2 it serves a dual function and is called SM0/FE. There are actually two
separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is
determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is accessed. When
SMOD0 is set to 0, then the SM0 flag is accessed.
The FE bit is set to 1 by the hardware but must be cleared by software. Once FE is set, any frames
received afterwards, even those without any errors, do not clear the FE flag. The flag has to be cleared
by software. Note that SMOD0 must be set to 1 while reading or writing to FE.
10.6 Multi-Processor Communications
Multi-processor communication makes use of the 9th data bit in modes 2 and 3. In the W78IRD2, the
RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware
feature eliminates the software overhead required in checking every received address and greatly
simplifies the software programmer task.
In multi-processor communication mode, the address bytes are distinguished from the data bytes by
the 9th bit, which is set high for address bytes. When the master processor wants to transmit a block of
data to one of the slaves, it first sends out the address of the target slave (or slaves). All the slave
processors should have their SM2 bit set high when waiting for an address byte. This ensures that they
are interrupted only by the reception of an address byte. The automatic address recognition feature
ensures that only the addressed slave is actually interrupted because the address comparison is done
by the hardware, not the software.
The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0,
the slave is interrupted on the reception of every single complete frame of data. The unaddressed
slaves are not affected, as they are still waiting for their address.
The Master processor can selectively communicate with groups of slaves by using the Given Address.
All the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined in the SADDR and SADEN registers. The slave address is an eight-bit value specified in
the SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in
SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives
the user flexibility to address multiple slaves without changing the slave address in SADDR.
The following example shows how the user can define the Given Address to address different slaves.
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