W78IRD2 Datasheet, PDF (14/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
Serial Port Control
Bit:
7
6
5
4
3
2
1
0
SM0/FE SM1 SM2 REN TB8 RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
Serial port, Mode 0 (SM0) bit or Framing-Error (FE) Flag: The SMOD0 bit in PCON
7
SM0/FE
SFR determines whether this bit acts as SM0 or as FE. SM0 is described with SMI1
below. When used as FE, this bit indicates whether the stop bit is invalid (FE=1) or
valid (FE=0). This bit must be manually cleared by software.
Serial port, Mode 1 (SM1) bit:
Mode: SM0 SM1 Description Length Baud rate
0
6 SM1
1
0 0 Synchronous 8 6(6T mode)/12(12T mode) T_clk
0 1 Asynchronous 10 Variable
2
1 0 Asynchronous 11 32/16(6T mode) or 64/32(12T mode) T_clk
3 1 1 Asynchronous 11 Variable
Multi-processor communication.
(Modes 2 and 3) Set this bit to enable the multi-processor communication feature.
With this feature, RI is not activated if the ninth data bit received (RB8) is 0.
5 SM2
(Mode 1) Set this bit to 1 to keep RI de-activated if a valid stop bit is not received.
(Mode 0) SM2 controls the serial port clock. If clear, the serial port runs at 1/12 the
oscillator. This is compatible with the standard 8052.
Receive enable:
4 REN 1 = Serial reception is enabled
0 = Serial reception is disabled
3
TB8
(Modes 2 and 3) This is the ninth bit to be transmitted. This bit is set and cleared by
software as desired.
(Modes 2 and 3) This is the ninth data bit that was received.
2 RB8 (Mode 1) If SM2 is 0, RB8 is the stop bit that was received.
(Mode 0) No function.
Transmit interrupt flag: This flag is set by the hardware at the end of the eighth bit in
1
TI mode 0 or at the beginning of the stop bit in modes 1 – 3 during serial transmission.
This bit must be cleared by software.
Receive interrupt flag: This flag is set by the hardware at the end of the eighth bit in
0
RI mode 0 or halfway through the stop bit in modes 1 – 3 during serial reception.
However, SM2 restricts this bit. This bit can be cleared only by software.
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