W78IRD2 Datasheet, PDF (51/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
12. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT)
The WDT is intended as a way to recover when the CPU may be subject to software problem. The
WDT consists of a 14-bit counter and the WDT reset (WDTRST) register located at 0A6H. The WDT is
disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to WDTRST.
Once the WDT is enabled, it increments every machine cycle, while the oscillator is running, and there
is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset).
The program must reset the counter by writing 01EH and 0E1H to WDTRST before the WDT counter
reaches 3FFFH (i.e., overflows). If it does overflow, it drives a HIGH pulse on the RST-pin. This pulse
width is 98 source clocks in 12-clock mode or 49 source clocks in 6-clock mode. No external pull-down
resistor or pull-up capacitor is required on the reset pin.
The WDT counter cannot be read or written. To make the best use of the WDT, the WDT should be
reset in sections of code that are periodically executed in time to prevent a WDT reset.
13. DUAL DPTR
The dual DPTR structure is the way the chip specifies the address of an external data memory
location. There are two 16-bit DPTR registers that address external memory. The DPS bit (AUXR1, bit
0) switches between them, and it can be toggled quickly by an INC AUXR1 instruction. (AUXR1, bit 2
cannot be written and is always read as a zero, so the INC AUXR1 instruction does not affect the GF2
bit that is higher in the AUXR1 register.)
It is important to keep track of the value of the DPS bit. For example, procedures and functions should
save the DPS bit before switching between DPTR0 and DPTR1 and restore the original value
afterwards to prevent other code from using the wrong memory.
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Publication Release Date: October 2, 2006
Revision A7