W78IRD2 Datasheet, PDF (43/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
Slave 1:
SADDR 1010 0100
SADEN 1111 1010
Given 1010 0x0x
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given address for slaves 1 and 2 differ in the LSB. For slave 1, it is a don't-care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate only
with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to
communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The
bit 3 position is don't-care for both the slaves. This allows two different addresses to select both slaves
(1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical OR of the SADDR and SADEN SFRs. The zeros in the result are
defined as don't cares. In most cases, the Broadcast Address is FFh. In the previous example, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at addresses A9h and B9h, respectively. On reset, these
registers are initialized to 00h. This results in Given Address and Broadcast Address being set as
XXXX XXXX(i.e. all bits don't care). This effectively removes the multi-processor communications
feature, since any selectivity is disabled.
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Publication Release Date: October 2, 2006
Revision A7