W78IRD2 Datasheet, PDF (19/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78IRD2
BIT NAME
FUNCTION
This register enables the Automatic Address Recognition feature of the serial port.
When a bit in SADEN is set to 1, the same bit in SADDR is compared to the
7~0 SADEN incoming serial data. When a bit in SADEN is set to 0, the same bit in SADDR is a
"don't care" value in the comparison. The serial port interrupt occurs only if all the
SADDR bits where SADEN is set to 1 match the incoming serial data.
On-Chip Programming Control
Bit:
7
6
5
4
3
SWRST/
REBOOT
-
-
-
-
Mnemonic: CHPCON Address: BFh
2
1
0
0 FBOOTSL FPROGEN
BIT
NAME
FUNCTION
When FBOOTSL and FPROGEN are set to 1, set this bit to 1 to force the
W: SWRESET microcontroller to reset to the initial condition, just like power-on reset. This
7 _{R: REBOOT action re-boots the microcontroller and starts normal operation.}
Read this bit to determine whether or not a hardware reboot is in progress.
6–2
1
0
-
FBOOTSL
FPROGEN
Reserved
Program Location Selection. This bit should be set before entering ISP
mode.
0: The Loader Program is in the 64-KB AP Flash EPROM. The 4-KB LD
Flash EPROM is the destination for re-programming.
1: The Loader Program is in the 4-KB memory bank. The 64-KB AP Flash
EPROM is the destination for re-programming.
FLASH EPROM Programming Enable.
1: Enable in-system programming mode. In this mode, erase, program and
read operations are achieved during device enters idle state.
0: Disable in-system programming mode. The on-chip flash memory is
read-only.
CHPCON has an unrestricted read access, however, the write access is protected by timed-access
protection. See the section of timed-access protection for more information.
External Interrupt Control
Bit:
7
6
5
4
3
2
1
0
PX3
EX3
IE3
IT3
PX2 EX2
IE2
IT2
Mnemonic: XICON Address: C0h
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Publication Release Date: October 2, 2006
Revision A7