MC3410 Datasheet, PDF (46/75 Pages) NXP Semiconductors – 10-Bit high-speed multiplying D/A converter

MC3410 3-Axis Accelerometer
Datasheet
11.4 INTEN: INTERRUPT ENABLE REGISTER
The interrupt enable register enables or disables interrupts on various motion events. If the
corresponding interrupt enable bit is set, a matching event will generate an interrupt transition
on the external interrupt pin, INTN. To enable the drop interrupt, set the DINT control bit in the
DROP: Drop Event Control Register.
When an interrupt is triggered, the first I2C access to the device will clear the external interrupt
pin, but the condition (TAPD, SHAKED, DROPD) that generated the interrupt will remain held
in the TILT: Status Register until it is read. Note that the orientation bit-fields POLA and BAFR
are continuously updated (every sample) in the TILT: Status Register and are not held.
Addr Name Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR R/
Value W
0x06
INTEN
Interrupt Enable
Register
SHINTX
SHINTY
SHINTZ
GINT
Resv
TINT PLINT FBINT 0x00 W
FBINT
PLINT
TINT
Resv
GINT
SHINTX
SHINTY
SHINTZ
Front / Back Interrupt
0: Disable interrupt on front/back position change
1: Enable interrupt on front/back position change
Portrait / Landscape Interrupt
0: Disable interrupt on up/down/left/right position change
1: Enable interrupt on up/down/left/right position change
Tap Interrupt
0: Disable interrupt on tap detection
1: Enable interrupt on tap detection
Reserved
Generate Interrupt
0: Disable automatic interrupt after each measurement
1: Enable automatic interrupt after each measurement is updated in XOUT, YOUT,
or ZOUT. The interrupt occurs for each measurement, not value change. See
Section 8.3.
Shake Interrupt, X-axis
0: Disable X-axis interrupt, SHAKED is not set in TILT: Status Register upon event
1 : Enable X-axis interrupt, SHAKED is set in TILT: Status Register upon event
Shake Interrupt, Y-axis
0: Disable Y-axis interrupt, SHAKED bit is not set in TILT: Status Register upon
event
1 : Enable Y-axis interrupt, SHAKED bit is set in TILT: Status Register upon event
Shake Interrupt, Z-axis
0: Disable Z-axis interrupt, SHAKED bit is not set in TILT: Status Register upon
event
1 : Enable Z-axis interrupt, SHAKED bit is set in TILT: Status Register upon event
Table 26. Interrupt Enable Register Settings
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APS-048-0010v2.2
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