C8051F310 Datasheet, PDF (68/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See Section “13.1. Priority Crossbar Decoder” on
page 127 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V_DD) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Table 7.1.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current.
See Table 7.1 for complete timing and current consumption specifications.
CMX1N1
CMX1N0
CMX1P1
CMX1P0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
VDD
CP1
Interrupt
P1.2
P1.6
P2.2
P2.6
P1.3
P1.7
P2.3
P2.7
CP1
Rising-edge
CP1
Falling-edge
CP1 +
CP1 -
+
-
GND
D ^SET Q
Q
CLR
D ^SET Q
Q
CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP1RIE
CP1FIE
Interrupt
Logic
CP1
Crossbar
CP1A
CP1MD1
CP1MD0
Figure 7.2. Comparator1 Functional Block Diagram
68
Rev. 1.6