C8051F310 Datasheet, PDF (67/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
7. Comparators
C8051F31x devices include two on-chip programmable voltage comparators: Comparator0 is shown in
Figure 7.1; Comparator1 is shown in Figure 7.2. The two comparators operate identically with the following
exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be
used as a reset source.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output with the device
in STOP mode. When assigned to a Port pin, the Comparator output may be configured as open drain or
push-pull (see Section “13.2. Port I/O Initialization” on page 129). Comparator0 may also be used as a
reset source (see Section “9.5. Comparator0 Reset” on page 106).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 7.5). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “13.3. General Purpose Port I/O” on page 131).
CMX0N1
CMX0N0
CMX0P1
CMX0P0
P1.0
P1.4
P2.0
P2.4
P1.1
P1.5
P2.1
P2.5
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
VDD
CP0
Interrupt
CP0
Rising-edge
CP0
Falling-edge
CP0 +
CP0 -
+
-
GND
D ^SET Q
Q
CLR
D ^SET Q
Q
CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP0RIE
CP0FIE
Interrupt
Logic
CP0
Crossbar
CP0A
CP0MD1
CP0MD0
Figure 7.1. Comparator0 Functional Block Diagram
Rev. 1.6
67