C8051F310 Datasheet, PDF (157/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
14.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to
the SMBus specification.
Table 14.4. SMBus Status Decoding
Values Read
Current SMbus State
Typical Response Options
Values
Written
1110
0
0
X
A master START was
generated.
Load slave address + R/W into
SMB0DAT.
00X
A master data or address byte Set STA to restart transfer.
0 0 0 was transmitted; NACK
received.
Abort transfer.
10X
01X
Load next data byte into
SMB0DAT.
00X
End transfer with STOP.
01X
1100
A master data or address byte End transfer with STOP and start
0 0 1 was transmitted; ACK
another transfer.
1
1
X
received.
Send repeated START.
10X
Switch to Master Receiver Mode
(clear SI without writing new data 0 0 X
to SMB0DAT).
Acknowledge received byte; Read
SMB0DAT.
0
0
1
Send NACK to indicate last byte,
and send STOP.
010
Send NACK to indicate last byte,
and send STOP followed by
START.
110
1000
1
0
X
A master data byte was
received; ACK requested.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
101
100
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
001
Send NACK and switch to Master
Transmitter Mode (write to
000
SMB0DAT before clearing SI).
Rev. 1.6
157