C8051F310 Datasheet, PDF (108/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
Table 9.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
RST Output Low Voltage
I_OL = 8.5 mA, V_DD = 2.7 to 3.6 V
RST Input High Voltage
Min Typ
—
—
0.7 x
V_DD
—
RST Input Low Voltage
—
—
RST Input Pullup Current
RST = 0.0 V
—
25
V_DD Monitor Threshold (V_RST)
2.40 2.55
Missing Clock Detector Timeout
Time from last system clock rising
edge to reset initiation
100
220
Reset Time Delay
Delay between release of any
reset source and code execution 5.0 —
at location 0x0000
Minimum RST Low Time to
Generate a System Reset
V_DD Monitor Turn-on Time
V_DD Monitor Supply Current
V_DD Ramp Time
V_DD = 0 V to V_DD = 2.7 V
15 —
100 —
—
20
—
—
Max
0.6
—
0.3 x
V_DD
40
2.70
600
—
—
—
50
1
Units
V
V
µA
V
µs
µs
µs
µs
µA
ms
108
Rev. 1.6