C8051F310 Datasheet, PDF (33/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
1.7. 10-Bit Analog to Digital Converter
The C8051F310/1/2/3/6 devices include an on-chip 10-bit SAR ADC with a 25-channel differential input
multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit accuracy with an INL of
±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and nega-
tive ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Temperature Sensor
output and the power supply voltage (V_DD) are available as ADC inputs. User firmware may shut down the
ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
P1.0
P1.6, P1.7 available on
C8051F310/1/2/3/4/5
P1.7
P2.0
P2.6, P2.7 available on
C8051F310/1/2/3/4/5
P3.1-3.4
available on
C8051F310/2
Temp
Sensor
P2.7
P3.0
P3.4
VDD
P1.0
P1.6, P1.7 available on
C8051F310/1/2/3/4/5
P1.7
P2.0
P2.6, P2.7 available on
C8051F310/1/2/3/4/5
P3.1-3.4
available on
C8051F310/2
P2.7
P3.0
P3.4
VREF
GND
23-to-1
AMUX
23-to-1
AMUX
Configuration, Control, and Data Registers
000
Start
Conversion ⁰⁰¹
010
011
100
101
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
10-Bit
(+)
SAR
(-)
ADC
ADC Data
16
Registers
End of
Conversion
Interrupt
Window Compare
Logic
Window
Compare
Interrupt
Figure 1.15. 10-Bit ADC Block Diagram
Rev. 1.6
33