C8051F310 Datasheet, PDF (31/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
1.4. Programmable Digital I/O and Crossbar
C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port);
C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F316/7
devices include 21 I/O pins (one byte-wide Port, two 6-bit-wide Ports and one 1-bit-wide Port). The
C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config-
ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for
push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally
disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.13).
On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
CP1
2
Outputs
SYSCLK
PCA
6
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
4
(P2.0-P2.3)
P2
4
(P2.4-P2.7)
5
P3 _(P3.0-P3.4)
Priority
Decoder
8
P0
I/O
Cells
Digital
Crossbar
8
P1
I/O
Cells
4
8
4
5
P2
I/O
Cells
P3
I/O
Cells
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
Notes:
1. P3.1–P3.4 only available on the
C8051F310/2/4.
2. P1.6, P1.7, P2.6, P2.7 only
available on the C8051F310/1/2/3/4/5
Figure 1.13. Digital Crossbar Diagram
Rev. 1.6
31