C8051F310 Datasheet, PDF (119/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
SFR Definition 12.3. CLKSEL: Clock Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
CLKSL0 00000000
Bit0 SFR Address:
0xA9
Bits7–1:
Bit0:
Reserved. Read = 0000000b, Must Write = 0000000.
CLKSL0: System Clock Source Select Bit.
0: SYSCLK derived from the Internal Oscillator, and scales per the IFCN bits in register
OSCICN.
1: SYSCLK derived from the External Oscillator circuit.
Table 12.1. Internal Oscillator Electrical Characteristics
V_DD = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Internal Oscillator Frequency
Internal Oscillator Supply
Current (from V_DD)
OSCICN.7 = 1
Min Typ Max
24 24.5 25
— 450 1000
Units
MHz
µA
Rev. 1.6
119