C8051F310 Datasheet, PDF (136/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

C8051F310/1/2/3/4/5/6/7
SFR Definition 13.11. P2: Port2
R/W
P2.7
Bit7
R/W
P2.6
Bit6
R/W
P2.5
Bit5
R/W
P2.4
Bit4
R/W
P2.3
Bit3
R/W
P2.2
Bit2
R/W
R/W
Reset Value
P2.1
P2.0 11111111
Bit1
Bit0 SFR Address:
(bit addressable) 0xA0
Bits7–0:
P2.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Always reads ‘1’ if selected as analog input in register P2MDIN. Directly reads Port
pin when configured as digital input.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
Note: Only P2.0–P2.5 are associated with Port pins on the C8051F1316/7 devices.
SFR Definition 13.12. P2MDIN: Port2 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF3
Bits7–0:
Analog Input Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P2.n pin is configured as an analog input.
1: Corresponding P2.n pin is not configured as an analog input.
Note: Only P2.0–P2.5 are associated with Port pins on the C8051F1316/7 devices.
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Rev. 1.6