C8051F310 Datasheet, PDF(105/224 Page) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

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C8051F310 Datasheet, PDF (105/224 Pages) List of Unclassifed Manufacturers – 8/16 kB ISP Flash MCU Family

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C8051F310/1/2/3/4/5/6/7

any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the

VDD monitor will still be enabled after the reset.

Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the

VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-

dure for configuring the VDD monitor as a reset source is shown below:

Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = â1â).

Step 2. Wait for the VDD monitor to stabilize (see Table 9.1 for the VDD Monitor turn-on time).

Note: This delay should be omitted if software contains routines that erase or write Flash

memory.

Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = â1â).

See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.

See Table 9.1 for complete electrical characteristics of the VDD monitor.

SFR Definition 9.1. VDM0CN: VDD Monitor Control

R/W

VDMEN

Bit7

R

R

R

R

R

R

R

Reset Value

VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xFF

Bit7:

Bit6:

Bits5â0:

VDMEN: VDD Monitor Enable.

This bit is turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system

resets until it is also selected as a reset source in register RSTSRC (Figure 9.2). The VDD

Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the

VDD monitor as a reset source before it has stabilized may generate a system reset.

See Table 9.1 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled.

VDD STAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD monitor threshold.

1: VDD is above the VDD monitor threshold.

Reserved. Read = Variable. Write = donât care.

9.3. External Reset

The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-

ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST

pin may be necessary to avoid erroneous noise-induced resets. See Table 9.1 for complete RST pin spec-

ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

Rev. 1.6

105

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