GMZAN3 Datasheet, PDF (44/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
HCLK
HFS
DEVICE ADDRESS
R/W ACK
OPERATION CODE
ACK
REGISTER ADDRESS
ACK
DEVICE ADDRESS
R/W ACK
DATA
DATA
ACK
DATA
START
START
STOP
Figure 28.
2-Wire Read Operation (0x9x and 0xAx)
Please note that in all the above operations the operation code includes two address bits, as described in
Table 20.
4.15.3 8-bit Parallel Interface
The 8-bit parallel interface connects to the external 8051 microcontroller’s external memory interface
utilizing the following signals: AD[7..0], ALE, WR#, RD#. An additional input signal (REG_MEM) is
used to distinguish between the register set and the OSD SRAM. When REG_MEM is held low the
gmZAN3 register set is selected and when it is held high the OSD SRAM will be active. The bus timing
requirements are given in Table 27 and Table 28. The OSD SRAM is R/W accessed in “pages” of 256
bytes.
The ALE signal is used to latch the 8-bits of address on the microprocessor’s multiplexed Address/Data
bus.
MCU
AD[7..0]
ALE
RDn
WRn
Output Port
ZAN3
AD[7..0]
ALE
RDn
WRn
MEM_REG
Figure 29.
8-bit Parallel Interface
C0523-DAT-01G
44
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003