GMZAN3 Datasheet, PDF (36/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
• Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to
display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display
timing is determined only by the values programmed into the display window and timing registers.
4.8.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an external
display device. Based on values programmed in registers, the Display Output Port produces the
horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals, which are then
encoded into the LVDS data stream by the on-chip LVDS transmitter. The figure below provides the
registers that define the output display timing.
Horizontal values are programmed in single pixel increments relative to the leading edge of the horizontal
sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical
sync signal.
DH_BKGND_START
DH_BKGND_END
VSYNC Region
Vertical Blanking (Back Porch)
Display Background Window
DV_VS_END
DV_BKGND_START
DV_ACTIVE_START
Display Active Window
DV_ACTIVE_LENGTH
DHS
DEN **
DH_HS_END
DH_ACTIVE_START
Vertical Blanking (Front Porch)
DH_TOTAL
DH_ACTIVE_WIDTH
DV_BKGND_END
** DEN is not asserted during vertical blanking
Figure 21.
Display Windows and Timing
The double-wide (TTL only) output only supports an even number of horizontal pixels.
C0523-DAT-01G
36
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003