GMZAN3 Datasheet, PDF (15/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
Pin Name
Table 5. Display Output Port for (gmZAN3L)
No I/O Description
DCLK
73 O
Not required. Panel output clock. Can be used for test purposes
[Tri-state output, Programmable Drive]
DVS
72 O
Not required. Panel Vertical Sync. Can be used for test purposes
[Tri-state output, Programmable Drive]
DHS
71 O
Not required. Panel Horizontal Sync. Can be used for test purposes
[Tri-state output, Programmable Drive]
DEN
70 O
Not required. Panel Display Enable, which frames the output background. Can be used for
test purposes
[Tri-state output, Programmable Drive]
PBIAS
77
O Panel Bias Control (back light enable)
PPWR
CH3P_LV
CH3N_LV
CLKP_LV
CLKN_LV
CH2P_LV
CH2N_LV
CH1P_LV
CH1N_LV
CH0P_LV
CH0N_LV
74
O Panel Power Control
6
O
LVDS Channel 3 positive¹
7
O
LVDS Channel 3 negative¹
8
O
LVDS Clock positive¹
9
O
LVDS Clock negative¹
10
O
LVDS Channel 2 positive¹
11
O
LVDS Channel 2 negative¹
12
O
LVDS Channel 1 positive¹
13
O
LVDS Channel 1 negative¹
14
O
LVDS Channel 0 positive¹
15
O
LVDS Channel 0 negative¹
Note: ¹These pin names are based on having swapping enabled on the initial positive and negative LVDS signals.
C0523-DAT-01G
15
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003