GMZAN3 Datasheet, PDF (23/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
Maximum Duty Cycle
40-60
4.1.3 Clock Synthesis
The gmZAN3 synthesizes all additional clocks internally as illustrated in Figure 9 below. The synthesized
clocks are as follows:
1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from
the TCLK/XTAL pad input.
2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference.
3. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC as the
reference. The SDDS internal digital logic is driven by RCLK.
4. ADC Output Clock (ACLK) is a delay-adjusted ADC sampling clock, ACLK. ACLK is derived from
SCLK.
5. Host Port Clock for OSD SRAM and muxed A/D port. TCLK at power up, and selectable as RCLK/2
or RCLK/4.
TCLK
HSYNC
RCLK
PLL
SDDS
DDDS
SCLK
÷4
÷2
M
U
X
ACLK
DCLK
HOST_CLK
for muxed A/D
8051 interface
Figure 9.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks. These include:
1. ADC Domain Clock (ACLK) which is also the input clock. Max = 100MHz
2. Host Interface (HOST_CLK). Max = 120MHz
3. Scaler and Display Pixel Clock (DP_CLK). Max = 100MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
C0523-DAT-01G
23
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003