GMZAN3 Datasheet, PDF (34/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
4.5.3 Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed
timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any VSYNC period
exceeds the programmed timing threshold (in terms of HSYNC pulses), a second register bit is set. An
interrupt can also be programmed to occur.
4.5.4 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user specifies start
and end values to outline a “window” relative to HSYNC. If the VSYNC leading edge occurs within this
window, the IFM signals the start of an ODD field. If the VSYNC leading edge occurs outside this
window, an EVEN field is indicated (the interpretation of odd and even can be reversed). The window
start and end points are selected from a predefined set of values.
HS
window
Window
Start
VS - even
VS - odd
Figure 20.
Window End
ODD/EVEN Field Detection
4.5.5 Input Pixel Measurement
The gmZAN3 provides a number of pixel measurement functions intended to assist in configuring system
parameters such as ACLK frequency (sample clocks per line) and phase setting, centering the image, or
adjusting the contrast and brightness.
4.5.6 Image Phase Measurement
This function measures the sampling phase quality over a selected active window region. This feature
may be used when programming the source DDS to select the proper phase setting.
4.5.7 Image Boundary Detection
The gmZAN3 performs measurements to determine the image boundary. This information is used when
programming the Active Window and centering the image.
4.5.8 Image Auto Balance
The gmZAN3 performs measurements on the input data that is used to adjust brightness and contrast.
C0523-DAT-01G
34
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003