GMZAN3 Datasheet, PDF (29/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
B
G
R
HS
SCLK
ACLK
Phase Delay
input HS
SDDS
Input Analog
Video
BLUE
GREEN
RED
ACLK
SCLK
Input HSync
SCLK
ACLK
Figure 14.
Phase
Delay
gmZAN3 Clock Recovery
4.3.4 Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the (input HSYNC aligned) SCLK to
produce the ADC clock (ACLK) inside the SDDS. The phase delay is programmable in 64 steps as a
fraction of the ACLK period. The accuracy of the sampling phase is checked and the result read from a
register. This feature enables accurate auto-adjustment of the ADC sampling phase.
4.3.5 Integrated Schmitt Trigger for Horizontal and Vertical Sync input
The gmZAN3 has integrated Schmitt triggers for Horizontal and Vertical Sync inputs, pin 85 and pin 86.
This allows for less number of components on the system board. It enables easier PCB layout, more
reliability and results in reducing the overall BOM cost.
The programmable hysteresis value is either 0.5V or 1.5V
C0523-DAT-01G
29
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003