GMZAN3 Datasheet, PDF (14/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
Pin Name
Table 4. System Interface and GPIO Signals (gmZAN3L)
No I/O Description
RESETn
RESET_OUT
GPIO0/PWM0
GPIO1/PWM1
GPIO2
GPIO3/IRQn
GPIO4/MEM_REG
GPIO5/AD7
GPIO6/AD6
GPIO7/AD5
GPO8
GPO9
GPO10
GPO11
GPO12
GPO13
HDATA0/ADO/HP0
HDATA1/AD1/HP1
HDATA2/AD2/OSC_SEL
HDATA3/AD3
HFS/AD4
HCLK/ALE
WRn
RDn
1 IO
Active-low hardware reset signal. The reset signal is held low for at least 150ms on the
chip power up. It has an internal 60KΩl pull-up resistor which can be used for re-setting
other system devices. See section 4.2
[Bi-directional (open drain), 5V-tolerant]
2O
Active-high hardware reset signal. The reset signal is held high for at least 150ms on the
chip power up. It can be used for re-setting other system devices[Output, 5V-tolerant]
80 IO
General-purpose input/output signal or PWM0. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
79 IO
General-purpose input/output signal or PWM1. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
78 IO
General-purpose input/output signal. Open drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
116 IO
General-purpose input/output signal. This is also active-low interrupt input external micro-
controller.
[Bi-directional, Active low open drain, 5V-tolerant]
117 IO-PD General-purpose input/output signal. Open drain option via register setting. For 8-bit A/D
host interface, this selects between OSD memory (high) and register access (low).
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pull-
down]
121 IO
General-purpose input/output signal or Adddress/data[7] for 8-bit A/D host interface. Open
drain option via register setting.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
122 IO
General-purpose input/output signal or Adddress/data[6] for 8-bit A/D host interface.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
123 IO
General-purpose input/output signal or Adddress/data[5] for 8-bit A/D host interface.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
60 O
General-purpose output signal.
63 O
General-purpose output signal.
52 O
General-purpose output.
53 O
General-purpose output signal.
40 O
General-purpose output signal.
43 O
General-purpose output signal.
128 IO-PD Host data for 6-wire serial protocol.
127
For 8-bit A/D host interface determines AD0 and AD1 bit.
Note: See Table 19, Boostrap Signals
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pull-
down]
126 IO-PD If using 6-wire protocol the HDATA[2] determines bit 2 of the host data. For 8-bit A/D host
interface determines AD2 bit.
Note: See Table 19, Boostrap Signals
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pull-
down]
125 IO-PD If using 6-wire protocol the HDATA[3] determines the upper AD3 bits of the host data. For
8-bit A/D host interface determines address/data bit.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pull-
down]
124 IO
Host Frame Sync. Frames the packet on the serial channel 6-wire interface. For 8-bit A/D host
interface determines AD4 bit.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V-tolerant]
118 I
Clock signal input for the 6-wire interface and 2-wire modes.
For 8-bit A/D host interface it becomes the Address Latch Enable.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
119 I-PU
For 8-bit A/D host interface write strobe input. Internal 60KΩ pull-up.
120 I-PU
For 8-bit A/D host interface read strobe input. Internal 60KΩ pull-up.
C0523-DAT-01G
14
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003