GMZAN3 Datasheet, PDF (42/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
4.15.1 Host Interface Command Format – for 2 or 6-wire
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two nibbles
respectively). These form an instruction byte, a device register address and/or one or more data bytes.
This is described in Table 20.
The first byte of each transfer indicates the type of operation to be performed by the gmZAN3. The table below
lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte
will vary depending on the instruction chosen. By utilizing these modes effectively, registers can be quickly
configured.
The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 20 below, are bits 9 and 8 of the
internal register address respectively. Thus, they should be set to ‘00’ to select a starting register address
of less than 256, ‘01’ to select an address in the range 256 to 511, and '10' to select an address in the range
512 to 767. These bits of the address increment in Address Increment transfers. The unused bits in the
instruction byte, denoted by 'x', should be set to ‘1’.
Bit
765432 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Table 20. Instruction Byte Map
Operation Mode
Description
Write Address Increment
Write Address No Increment
(for table loading)
Read Address Increment
Read Address No Increment
(for table reading)
Reserved
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
Spare
No operation will be performed
4.15.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK and bi-directional serial data line HFS. The bus
master drives HCLK and either the master or slave can drive the HFS line (open drain) depending on
whether a read or write operation is being performed. The gmZAN3 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit slave address. The gmZAN3 is
initialized on power-up to 2-wire mode by asserting bootstrap pins HP[1:0] to “10” and the slave address
select bootstrap option HDATA3 on the rising edge of RESETn. By pulling HDATA3 high or low it is
possible to select one of the two slave addresses: 0x94 & 0x95 (for HDATA=1) or 0x70 & 0x71 (for
HDATA=0). This provides flexibility to configure the system consisting of multiple devices with the
same slave address.
C0523-DAT-01G
42
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003