GMZAN3 Datasheet, PDF (12/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
3 gmZAN3 Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground, I-PU = Input with pull-up,
I-PD = Input with pull down, IO-PD = Bidirectional with pull down
Table 1. Analog Input Port (Common to gmZAN3T and gmZAN3L)
Pin Name No. I/O Description
AVDD_RED_3.3
RED+
RED-
AGND_RED
AVDD_GREEN_3.3
SOG_MCSS
GREEN+
GREEN-
AGND_GREEN
AVDD_BLUE_3.3
BLUE+
BLUE-
AGND_BLUE
AVDD_ADC_3.3
96 AP
97 AI
98 AI
99 AG
91 AP
92 AI
93 AI
94 AI
95 AG
87 AP
88 AI
89 AI
90 AG
100 AP
ADC_TEST
AGND_ADC
GND_ADC
VDD_ADC_1.8
HSYNC
VSYNC
101 AO
102 AG
103 AG
104 P
85 I
86 I
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor
(0.1µF) to AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor
(0.1µF) to AGND_GREEN pin on system board (as close as possible to the pin).
Dedicated Sync-on-Green pin
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor
(0.1µF) to AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor (0.1µF) to AGND_ADC pin on system board (as close as possible to
the pin).
Analog test output for ADC. Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to system ground plane.
Digital ground for ADC clocking circuit.
Must be directly connected to the system ground plane.
Digital power (1.8V) for ADC encoding logic. Must be bypassed with decoupling capacitor
(0.1µF) to GND_ADC pin on system board (as close as possible to the pin).
ADC input horizontal sync input. The input hysteresis can be set to 0.5V or 1.5V
[Input, Schmitt trigger, 5V-tolerant]
ADC input vertical sync input. The input hysteresis can be set to 0.5V or 1.5V
[Input, Schmitt triggered, 5V-tolerant]
Pin Name
TCLK
XTAL
VBUFS_RPLL
AVSS_RPLL
VSS_RPLL
VDD_RPLL_1.8
AVDD_RPLL_3.3
Table 2. Clock Pins (Common to gmZAN3T and gmZAN3L)
No I/O Description
111 AI
110 AO
107 AO
108 G
105 G
106 P
109 P
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 5), or from single-
ended CMOS/TTL clock oscillator (see Figure 8). This is a 5V-tolerant input. See Table 14.
Crystal oscillator output.
Reserved. For test purposes only. Do not connect
Analog ground for the reference DDS PLL. Must be directly connected to the system ground
plane.
Digital ground for the RCLK and clock generator. Must be directly connected to the system
ground plane.
Digital power for the RCLK and clock generators. Connect to 1.8V supply. Must be bypassed
with a 0.1µFcapacitor to pin AVSS_RPLL
Analog power for the reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1µFcapacitor to pin VSS_RPLL
C0523-DAT-01G
12
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003