GMZAN3 Datasheet, PDF (28/53 Pages) List of Unclassifed Manufacturers – XGA ALALOG INTERFACE LCD MONITOR CONTROLLER

gmZAN3 Preliminary Data Sheet
4.3.2 ADC Characteristics
The table below summarizes the characteristics of the ADC:
Table 15. ADC Characteristics
Track & Hold Amp Bandwidth
MIN
Full Scale Adjust Range at RGB Inputs 0.55 V
Full Scale Adjust Sensitivity
Zero Scale Adjust Sensitivity
Sampling Frequency (Fs)
Differential Non-Linearity (DNL)
No Missing Codes
Integral Non-Linearity (INL)
Channel to Channel Matching
10 MHz
TYP
+/- 1 LSB
+/- 1 LSB
+/-0.5 LSB
+/- 1.5 LSB
+/- 0.5 LSB
MAX
NOTE
290 MHz Guaranteed. Note that the Track & Hold Amp
Bandwidth is programmable. 290 MHz is the
maximum setting.
0.90 V
Measured at ADC Output.
Independent of full scale RGB input.
Measured at ADC Output.
100 MHz
+/-0.9 LSB Fs = 100 MHz
Guaranteed by test.
Fs =100 MHz
Note that input formats with resolutions or refresh rates higher than that supported by the LCD panel are
supported as recovery modes only. This is called RealRecovery™. For example, it may be necessary to
shrink the image. This may introduce image artifacts. However, the image is clear enough to allow the
user to change the display properties.
The gmZAN3 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors
(about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and
width are programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample
analog RGB data (ACLK). This circuit is locked to HSYNC of the incoming video signal.
Patented digital clock synthesis technology makes the gmZAN3 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit
can generate any ACLK clock frequency within the range of 10 MHz to 100 MHz.
C0523-DAT-01G
28
Genesis Microchip Confidential
http://www.genesis-microchip.com
July 2003